Electronic designs may be large systems that include millions of gates and megabits of embedded memory. Of the tasks required in managing and optimizing electronic designs, synthesis, placement, and routing utilizing available resources can be among the most challenging and time consuming. The complexity of large systems often requires the use of electronic design automation (EDA) tools to manage and optimize designs. EDA tools perform the time-consuming tasks of synthesis, placement, and routing.
Some EDA tools allow users to specify long-path timing constraints such as, for example, FMAX (maximum clocking frequency), TSU (setup time), and TCO (clock-to-output time), in order for designs to meet performance targets. However, many of these EDA tools do not take into account short-path timing constraints.
One vehicle for the implementation of semiconductor designs is to use programmable logic devices (PLDs). PLDs are structured semiconductor devices that include programmable logic, programmable routing, embedded memory, etc. Through appropriate programming, PLDs can be used to implement a variety of logic designs.
At the periphery of a PLD, there are board-level long-path and short-path timing constraints that must be satisfied. Historically, since EDA tools do not take into account short-path timing constraints, users had to manually repair the technology mapping, placement, and routing of the design, or redesign the entire system to satisfy these board-level timing constraints.
Also, PLDs typically provide a number of dedicated clock networks which facilitate operation on a device without encountering internal hold-time violations (violations between registers in the PLD). However, with larger designs where a sufficient number of dedicated clock networks are not available on a PLD, a design may require that clocks be routed locally. In these instances, if a hold-time violation occurred, the user had to manually repair the technology mapping, placement or routing of the design or redesign the entire system. This could be both difficult and time consuming.
Thus, what is needed is an EDA tool that is able to perform the tasks of technology mapping, placement and routing in response to long-path and short-path timing constraints.